The invention relates to a semiconductor memory circuit having memory cells which are arranged in columns and rows and which can be connected to a read amplifier by means of selection means, an output of the said amplifier driving a tristate bus driver, two bit lines, to which a column of memory cells is connected, being connected to a supply line via P-MOS pull-up transistors and being fed to an input and to an inverting input of a difference amplifier.
Such a semiconductor memory circuit is known from ISSCC 1984, Feb. 23, pp. 214-215 and 340, in which it was stated that delay times occurring in word and bit lines and also in read amplifiers and bus drivers are of vital importance for memory circuits of large capacity (for example, 256 k bit). A small dissipated power in a memory of comparatively large capacity is also of importance.